2020 | SDRAM : Secure Dynamic ReAl-time Memory hierarchy

Axe : Scilex
Sujet : Scilex-1 Security of systems

Directrice de thèse : Lirida Naviner
Encadrants : Florian Brandner, Mihail Asavoae
Laboratoire gestionnaire : LTCI (Télécom Paris)
Autres partenaires : SATI (Université Paris-Saclay), CEA List
Doctorant : Felipe Lisboa
Début : 2020
Productions scientifiques :
Ressources :

Contexte : Critical systems typically have to meet strict regulations that, aside from function correctness, also cover non-functional properties, e.g., timeliness of the computed results and reliability against faults. In multi-criticality real-time systems, (safety-)critical tasks share a computing platform with non-critical computations. Critical tasks thus have to be isolated from other tasks in the system, both, in terms of timeliness (contention on shared resources) and security (information leaks or attacks). The memory hierarchy of modern multi-core computer architectures poses many challenges to such systems, since temporal isolation has to be ensured, while achieving high performance, and data has to be protected,while enabling sharing. Starting from recent results in time-predictable bus arbitration, this proposal aims at exploring security and predictability considerations of the bus design itself, but also its interfaces to (shared) caches and the underlying DDR memory.